High-Speed Area-Efficient VLSI Architecture
[View]
1P Renuka,2Badugu Sai Kumar,3Abhiram Vasipalli,4Appasani Bhargav,5Chidipothu Giri,6Dunnapothula Sreekanth
Addition is one of the most basic operations performed in all computing units, including microprocessors and digital signal processors
DOI: 30.8650/ijearst.28.76.9276
1P Renuka,2Badugu Sai Kumar,3Abhiram Vasipalli,4Appasani Bhargav,5Chidipothu Giri,6Dunnapothula Sreekanth
Addition is one of the most basic operations performed in all computing units, including microprocessors and digital signal processors
DOI: 30.8650/ijearst.28.76.9276
AxBMs Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators
[View]
1P Renuka,2Shaik Uppalapati Rasool,3Gogulapati Sudheer,4Jogi Hemantha Tataji,5Karanki GopiVenkata Narasimha,6Shahid Ali Malgi
Consumption of Energy is the major factor, in the various processing application like DSP, ASIC, and FPGA. The motive of this work is to approximate the multiplication process
DOI:30.8090/ijearst.87.70.5988
1P Renuka,2Shaik Uppalapati Rasool,3Gogulapati Sudheer,4Jogi Hemantha Tataji,5Karanki GopiVenkata Narasimha,6Shahid Ali Malgi
Consumption of Energy is the major factor, in the various processing application like DSP, ASIC, and FPGA. The motive of this work is to approximate the multiplication process
DOI:30.8090/ijearst.87.70.5988
Design of Area Optimized Arithmetic and Logical 32bit
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1 M Madhavi,2 Ramachandrapu Saron,3 Mala Tharun,4 Proddutooru Sandeep,5 SaddalaRupesh,6 Ukkala Ajay Kumar
Digital design is an amazing and very broad field. The applications of digital design are present in our daily life, including Computers, calculators, video cameras etc
DOI:30.8064/ijearst.76.56.9747
1 M Madhavi,2 Ramachandrapu Saron,3 Mala Tharun,4 Proddutooru Sandeep,5 SaddalaRupesh,6 Ukkala Ajay Kumar
Digital design is an amazing and very broad field. The applications of digital design are present in our daily life, including Computers, calculators, video cameras etc
DOI:30.8064/ijearst.76.56.9747
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography
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1M Madhavi,2Kothapalli Nagendrachari,3Bonthu Ayyappa,4Jeeri Aditya,5B Sudhakaru,6BayyaMahesh
The VLSI implementation of the high-speed modular multiplier remains a big challenge.
DOI:30.1450/ijearst.44.59.6568
1M Madhavi,2Kothapalli Nagendrachari,3Bonthu Ayyappa,4Jeeri Aditya,5B Sudhakaru,6BayyaMahesh
The VLSI implementation of the high-speed modular multiplier remains a big challenge.
DOI:30.1450/ijearst.44.59.6568
Overloaded CDMA Crossbar for Network-On-Chip
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1 V V Krishna,2 Yerraballi Kumar Reddy,3 Koyalkar Naveen,4 Kummara Sumanth,5 LokanadhamBoddepalli,6 Saddala Yerri Swamy
Here, in this project; embedded transition inversion (ETI) is proposed to reduce bit transitions in Serializing parallel buses.
DOI:30.8310/ijearst.11.99.1572
1 V V Krishna,2 Yerraballi Kumar Reddy,3 Koyalkar Naveen,4 Kummara Sumanth,5 LokanadhamBoddepalli,6 Saddala Yerri Swamy
Here, in this project; embedded transition inversion (ETI) is proposed to reduce bit transitions in Serializing parallel buses.
DOI:30.8310/ijearst.11.99.1572
Efficient implementation of signed multipliers on FPGAs
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1V V KRISHNA,2K HEMESH,3J YOGENDRA REDDY,4KOTLA DEVENDRANATH BABU,5MUDAVAT RAMESH NAIK,6MURAM VENKATA SISINDRA REDDY
This project presents a simple but effective strategy to implement signed binary multipliers on ay hardware with low power consumption
DOI: 30.0485/ijearst.06.01.3478
1V V KRISHNA,2K HEMESH,3J YOGENDRA REDDY,4KOTLA DEVENDRANATH BABU,5MUDAVAT RAMESH NAIK,6MURAM VENKATA SISINDRA REDDY
This project presents a simple but effective strategy to implement signed binary multipliers on ay hardware with low power consumption
DOI: 30.0485/ijearst.06.01.3478
Lightweight Direct Memory Access on FPGAmaterial
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1 V V KRISHNA,2VESAPOGU KIRAN KUMAR RAJ,3HEMANADHA REDDDY MADARAM,4MSIDHARTHA REDDY,5T VENKATA SIVA,6SANA RAJASEKHAR
The project aims to design a soft core processor system with Advanced eXtensible Interface (AXI) processor bus which deals with different data capacities with 32, 64, 128, and 256 bits data width
DOI: 30.0485/ijearst.06.01.3478
1 V V KRISHNA,2VESAPOGU KIRAN KUMAR RAJ,3HEMANADHA REDDDY MADARAM,4MSIDHARTHA REDDY,5T VENKATA SIVA,6SANA RAJASEKHAR
The project aims to design a soft core processor system with Advanced eXtensible Interface (AXI) processor bus which deals with different data capacities with 32, 64, 128, and 256 bits data width
DOI: 30.0485/ijearst.06.01.3478
Design of a VLSI Router for the Faster_Data_Transmission_Using_Buffer
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1V V KRISHNA, 2MALLAVARAPU NAGARAJU,3ANAPALA PADALA REDDY, 4SHAIK ISMAIL,5KOLATAM RAJESH KUMAR,6V SUBRAMANYAM
The router is a” Network Router” has a one input port from which the packet enters. It has five output ports where the packet is driven out.
DOI: 30.0485/ijearst.06.01.3478
1V V KRISHNA, 2MALLAVARAPU NAGARAJU,3ANAPALA PADALA REDDY, 4SHAIK ISMAIL,5KOLATAM RAJESH KUMAR,6V SUBRAMANYAM
The router is a” Network Router” has a one input port from which the packet enters. It has five output ports where the packet is driven out.
DOI: 30.0485/ijearst.06.01.3478
Design and analysis of 16-bit RISC processor
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1M MADHAVI,2PADE ARUNA,3ITHADI SWAPNA,4ANDRA AKSHAYA,5MEDAPI ANJANILAKSHMI
This project describes a 16-bit RISC microprocessor core that has been designed for portable applications.
DOI: 30.0485/ijearst.06.01.3479
1M MADHAVI,2PADE ARUNA,3ITHADI SWAPNA,4ANDRA AKSHAYA,5MEDAPI ANJANILAKSHMI
This project describes a 16-bit RISC microprocessor core that has been designed for portable applications.
DOI: 30.0485/ijearst.06.01.3479
ECG Signal Filtering in FPGA
[View]
1P RENUKA,2NARUKURI NAGAMANI,3PASUPULETI VIJITHA,4SHAIK HUSSAINA,5THIRUMALASETTYBHARATHI
Electrocardiographic signal (ECG) is the most important electrophysiological signal used in the clinic for screening and diagnosis of many cardiac diseases.
DOI: 30.0485/ijearst.06.01.3478
1P RENUKA,2NARUKURI NAGAMANI,3PASUPULETI VIJITHA,4SHAIK HUSSAINA,5THIRUMALASETTYBHARATHI
Electrocardiographic signal (ECG) is the most important electrophysiological signal used in the clinic for screening and diagnosis of many cardiac diseases.
DOI: 30.0485/ijearst.06.01.3478
VLSI Implementation of Fast Addition Using Quaternary Signed Digit Number System
[View]
1P RENUKA,2NANGEDLA KALYANI,3BADUGU JUHI SRAVANTHI,4KOMMARA SRAVANI,5NBHAGYA LAKSHMI
High performance adders are essential since the speed of the digital processor depends heavily on the speed of the adders used is the system.
DOI: 30.0485/ijearst.06.01.3478
1P RENUKA,2NANGEDLA KALYANI,3BADUGU JUHI SRAVANTHI,4KOMMARA SRAVANI,5NBHAGYA LAKSHMI
High performance adders are essential since the speed of the digital processor depends heavily on the speed of the adders used is the system.
DOI: 30.0485/ijearst.06.01.3478
A wireless Framework for environmental Monitoring and Instance Response Alert
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1S.Raghava Rao,2Ankam Naga Srivalli,3Perabathula Satya Lavanya,4Molleti Meghana,5AdinipetaManikanta,6Vittanala Eswari
This paper proposes an advanced wireless framework for real-time environmental monitoring integrated with an instant response alert system.
DOI:30.7811/ijearst.70.06.7625
1S.Raghava Rao,2Ankam Naga Srivalli,3Perabathula Satya Lavanya,4Molleti Meghana,5AdinipetaManikanta,6Vittanala Eswari
This paper proposes an advanced wireless framework for real-time environmental monitoring integrated with an instant response alert system.
DOI:30.7811/ijearst.70.06.7625
Toward Designing High-Speed Cost-Efficient Quantum Reversible Carry Select Adders
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1 D.D. Saibaba,2 P. Saisri Lakshmi,3 A. Bhavana Laxmi,4 B. Ramanababu,5 G.S.S.N.V. Lakshmi
Reversible logic efficiently prevents energy wastage through thermal dissipation.
30.9502/ijearst.38.22.8114
1 D.D. Saibaba,2 P. Saisri Lakshmi,3 A. Bhavana Laxmi,4 B. Ramanababu,5 G.S.S.N.V. Lakshmi
Reversible logic efficiently prevents energy wastage through thermal dissipation.
30.9502/ijearst.38.22.8114
Design of Single-Architecture Universal Shift Register and Counter with Memory Unit using Full-Swing GDI D-Flip-Flops
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1 Vayara Prasanna Lakshmi,2 Balla Divya Tejaswi,3 Cheekatla Chishma Lakshmi AnanthaHyma,4 Podalada Ramya Sindhu,5 Appari Ramya Sri
This research presents a novel single-architecture universal shift register/counter with an integrated memory unit.
30.3353/ijearst.13.25.9936
1 Vayara Prasanna Lakshmi,2 Balla Divya Tejaswi,3 Cheekatla Chishma Lakshmi AnanthaHyma,4 Podalada Ramya Sindhu,5 Appari Ramya Sri
This research presents a novel single-architecture universal shift register/counter with an integrated memory unit.
30.3353/ijearst.13.25.9936
NARMAX Self-Tuning Controller for Line-of-Sight-Based Waypoint Tracking for an Autonomous Underwater Vehicle
[View]
1 Pechetti Girish,2 Bhogisetti Adithya,3 Gundumenu Manasa,4 Mamidikuduru Sravani Durga,5Chukkana Satya Venkata Padmaraju
Autonomous Underwater Vehicles (AUVs) require precise and robust control strategies to navigate complex
30.6251/ijearst.43.75.1453
1 Pechetti Girish,2 Bhogisetti Adithya,3 Gundumenu Manasa,4 Mamidikuduru Sravani Durga,5Chukkana Satya Venkata Padmaraju
Autonomous Underwater Vehicles (AUVs) require precise and robust control strategies to navigate complex
30.6251/ijearst.43.75.1453
Design of Area Optimized Arithmetic and Logical
[View]
1K.Jyothirmai,2Ramanaidu,3Deepthi,4A.Nandini,5K.Rakesh
Digital design is an amazing and very broad field.
30.5232/ijearst.35.72.4973
1K.Jyothirmai,2Ramanaidu,3Deepthi,4A.Nandini,5K.Rakesh
Digital design is an amazing and very broad field.
30.5232/ijearst.35.72.4973
LOW RANK DECOMPOSITION BASED RESTORATION OF COMPRESSED IMAGES VIA ADAPTIVE NOISE ESTIMATION
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1Dr. BH V V S R K K Pavan,2Gannavarapu Dhanalakshmi,3Kalidasu Satyaveni,4Payasam Y S SuryaLakshmi,5 Medidi Manikanta Sai
Images coded at low bit rates in real-world applications usually suffer from significant compression noise
30.9378/ijearst.75.86.7188
1Dr. BH V V S R K K Pavan,2Gannavarapu Dhanalakshmi,3Kalidasu Satyaveni,4Payasam Y S SuryaLakshmi,5 Medidi Manikanta Sai
Images coded at low bit rates in real-world applications usually suffer from significant compression noise
30.9378/ijearst.75.86.7188
A_VLSI-Based_Hybrid_ECG_Compression_Scheme_for_Wearable_Sensor_Node
[View]
1Dr. K. Sirisha,2Vadagana Lepakshi Santoshi,3Peddireddi Naga Satya Sri,4Kallakuri Susmitha,5LalamAbhinay
ECG (electrocardiogram) is a test that measures the electrical activity of the heart
30.5687/ijearst.83.74.7543
1Dr. K. Sirisha,2Vadagana Lepakshi Santoshi,3Peddireddi Naga Satya Sri,4Kallakuri Susmitha,5LalamAbhinay
ECG (electrocardiogram) is a test that measures the electrical activity of the heart
30.5687/ijearst.83.74.7543
diabetic retinopathy detection by extracting area and number of microaneurysm from colour fundus image
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1 M Ganeswara Rao,2 Kotipalli Pujitha Veera Sai Siri,3 Kalvakolanu Lakshmi Swathi,4 Govathoti Joel,5Kathimanda Jeevana Jyothi
Diabetic retinopathy (DR) is an intricacy of diabetes and a main source of vision misfortu
30.3704/ijearst.63.64.2437
1 M Ganeswara Rao,2 Kotipalli Pujitha Veera Sai Siri,3 Kalvakolanu Lakshmi Swathi,4 Govathoti Joel,5Kathimanda Jeevana Jyothi
Diabetic retinopathy (DR) is an intricacy of diabetes and a main source of vision misfortu
30.3704/ijearst.63.64.2437
An Effective Architecture of Memory Built-In Self-Test for Wide Range of SRAM
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1V.Harika,2Vanarasi Sri Satya Sai Naga Pushpa Latha,3M.Sowjanya Lakshmi,4D.Jahnavi sri satya,5S.Naveen babu
Testing semiconductor memories is increasingly important today because of the high density of current memory chips
30.3425/ijearst.41.93.5471
1V.Harika,2Vanarasi Sri Satya Sai Naga Pushpa Latha,3M.Sowjanya Lakshmi,4D.Jahnavi sri satya,5S.Naveen babu
Testing semiconductor memories is increasingly important today because of the high density of current memory chips
30.3425/ijearst.41.93.5471
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